How to choose STM32 clock?

Choosing the right clock configuration for an STM32 microcontroller is critical for balancing performance, power consumption, and peripheral requirements. Here’s a step-by-step guide to selecting and configuring the clock in STM32:

1. Understand STM32 Clock Sources

STM32 microcontrollers typically support these clock sources:

2. Key Clock Parameters to Configure

1. SYSCLK (System Clock)

   • Determines CPU speed (e.g., 72 MHz for STM32F1, 480 MHz for STM32H7).

   • Derived from HSE, HSI, or PLL.

2. AHB, APB1, APB2 Clocks

   • AHB: Fast bus for CPU, DMA, memory (usually = SYSCLK).

   • APB1: Low-speed peripherals (UART, I2C, SPI) – often half SYSCLK.

   • APB2: High-speed peripherals (GPIO, ADC, TIM1) – often equal to SYSCLK.

3. Peripheral Clocks

   • Some peripherals (USB, SDIO, RNG) require specific frequencies (e.g., 48 MHz for USB).

3. Step-by-Step Clock Configuration

Option A: Using STM32CubeMX (Recommended)

1. Open STM32CubeMX and select your MCU.

2. Navigate to Clock Configuration tab.

3. Choose a source for SYSCLK:

   • HSE (if using an external crystal).

   • HSI (if no crystal is available).

4. Configure PLL (if needed):

   • Example (STM32F4):

     • HSE = 8 MHz → PLL multiplies to 8 MHz × 9 = 72 MHz SYSCLK.

5. Set AHB, APB1, APB2 dividers (e.g., AHB = SYSCLK, APB1 = SYSCLK/2).

6. Verify flash latency (higher clocks may require more wait states).

Option B: Manual Configuration (Register-Level)

// Example for STM32F4 (72 MHz using HSE and PLL)
RCC->CR |= RCC_CR_HSEON;       // Enable HSE
while (!(RCC->CR & RCC_CR_HSERDY)); // Wait for HSE ready

// Configure PLL (8 MHz HSE → 72 MHz SYSCLK)
RCC->PLLCFGR = (8 << RCC_PLLCFGR_PLLM_Pos) |  // PLLM = 8 (HSE divider)
               (72 << RCC_PLLCFGR_PLLN_Pos) |  // PLLN = 72 (multiplier)
               (0 << RCC_PLLCFGR_PLLP_Pos);    // PLLP = 2 (SYSCLK divider)

RCC->CR |= RCC_CR_PLLON;       // Enable PLL
while (!(RCC->CR & RCC_CR_PLLRDY)); // Wait for PLL lock

// Set AHB = 72 MHz, APB1 = 36 MHz, APB2 = 72 MHz
RCC->CFGR |= RCC_CFGR_HPRE_DIV1 |   // AHB = SYSCLK
             RCC_CFGR_PPRE1_DIV2 |   // APB1 = SYSCLK/2
             RCC_CFGR_PPRE2_DIV1;    // APB2 = SYSCLK

RCC->CFGR |= RCC_CFGR_SW_PLL;        // Switch to PLL as SYSCLK

4. Clock Optimization Tips

• Power Saving: Use HSI + PLL for dynamic voltage scaling.

• USB Requirement: If using USB, ensure 48 MHz clock (from PLL).

• RTC: Requires LSE (32.768 kHz) for accurate timekeeping.

• Overclocking: Possible but risky (e.g., STM32F103 at 128 MHz).

5. Common Mistakes to Avoid

1. Incorrect PLL Settings → MCU crashes or runs slower.

2. Flash Latency Too Low → CPU stalls at high frequencies.

3. Peripheral Clock Mismatch (e.g., UART baud rate wrong due to APB divider).

6. Verify Your Configuration

• Use STM32CubeMX’s Clock Graph to visualize paths.

• Check RCC registers in debug mode (e.g., RCC->CFGR).

• Measure clocks with an oscilloscope (e.g., MCO pin output).

Example Configurations

Final Advice

• Start with STM32CubeMX for automatic clock setup.

• Refer to the datasheet for max frequencies and PLL constraints.

• Test stability by running peripherals (ADC, UART) at full speed.