Can Verilog and VHDL be improved for FPGAs?

What is the Verilog?

Actually, the origins of Verilog lie in Hilo, a dated hardware description language, and in the C programming languages. It is a very limited and weakly typed language because it contains all of the established data types. The datatypes are shown at the bit level. Other data types can be coupled with strings and Verilog. Verilog's simulation semantics are less precise than VHDLs'. Verilog is highly versatile for developers as a result, however, if coding rules are not followed, race scenarios may arise as a result of ambiguity. It is necessary to supply the reusability function of packages, however, this is extremely difficult due to the language's constrained scope and weak packaging ability. Verilog provides basic simulation control commands that help with system operations. Programmers typically use command-line or batch simulations due to Verilog's pre-defined system tasks and simple data formats. The simulation's waveforms can also be used for debugging.  

The history of Verilog

Cadence Design System, one of the largest providers of electronic design technologies and engineering services in the electronic design automation (EDA) sector, purchased Gateway Design Automation Inc. in 1990. Cadence appreciated Verilog's value and understood that if Verilog remained a closed language, standardization pressure would eventually force people to switch to VHDL. Therefore, Cadence created the Open Verilog International (OVI) (now known as Accellera) in 1991 and released the Verilog documentation into the public domain under the name of OVI. Later, it was submitted to IEEE, where it was accepted as IEEE standard 1364-1995, also known as Verilog-95. Extensions to Verilog-95 were resubmitted to the IEEE in 2001, and as a result, Verilog-2001, also known as IEEE Standard 1364-2001, was created. Some shortcomings in the Verilog-95 that users had discovered were addressed by the extensions. The support for signed variables (in 2.s complement) was one of the biggest improvements. Currently, the majority of design tools support Verilog-2001 as the standard edition of the language. Verilog-2005 (IEEE Standard 1364-2005), which has a few minor adjustments and modifications, was released in 2005. A superset of Verilog-2005 called System Verilog, which has a lot of new features and capabilities to help with design verification, was also introduced in 2005. One of the most widely used languages for IC design and verification today, SystemVerilog 2009 (IEEE Standard 1800-2009) was created in 2009 by combining the SystemVerilog and Verilog language standards. SystemVerilog is supported by the 2013-released Xilinx® Vivado Design Suite for FPGA design and verification.  

What is the VHDL?

VHDL truly has its roots in the programming language Ada, a very strongly typed and densely typed hardware description language. Due to the language requirement, VHDL is far more verbose than Verilog, another HDL, which also increases the quantity of self-documenting designs. In VHDL, strong typing ensures that explicit datatype transformations, such as from a bit-vector to an integer, take place. The VHDL language's semantics were designed to be exceptionally simple and unambiguous. VHDL designs are lightweight, which increases the functionality of switching from one tool to another with ease. As a result, there is no need to worry about racial issues. The VHDL design mainly relies on IEEE standard 1164 and also makes use of the Math and Numeric packages in order to boost the language's usability. VHDLs lack features for monitoring or simulation control and are entirely tool-dependent. Debugging design difficulties are more complex and necessitate the use of interactive GUIs because VHDL types are user-defined and there is no built-in simulation control.  

The history of VHDL

The entire FPGA community is making a lot of effort, but due to the nature of FPGAs, this task is challenging to complete. We must examine the initial intent of FPGAs in order to comprehend why this is the case. A full year after the debut of VHDL, in 1984, the FPGA manufacturer Xilinx was established. VHDL was initially created by the US military as a method of precisely describing how Application Specific Integrated Circuits (ASICs) behave. FPGAs were promoted by Xilinx as a solution to simulate ASICS' actions without having to create them beforehand. Since ASIC engineers were already using VHDL, Xilinx's tools naturally supported it. Because HDL attempts to map a circuit's behavior at the Register Transfer Level (RTL), it is challenging to use. This occurs when information in the form of electronic signals flows from one register to the next register within a predetermined period known as a clock cycle after passing through a series of logical gates. The designer utilizes VHDL to specify how billions of these signals should move during each clock cycle in a single ASIC. Since only experts can utilize it, it naturally takes them a long time to correctly simulate and debug FPGA designs.  

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Conventional FPGA Design Tools

Over the first 20 years of FPGA development, hardware description languages (HDLs) like VHDL and Verilog evolved to become the primary languages for designing the algorithms that run on the FPGA chip. With the knowledge that you are constructing a circuit on an FPGA, these low-level languages incorporate some of the benefits of existing textual languages. Signals from external I/O ports must be mapped or connected to internal signals before being sent to the functions that house the algorithms in order to use the resulting hybrid syntax. These concurrently operating processes have the ability to refer to other FPGA-based operations. However, a sequential line-by-line flow makes it challenging to comprehend the true parallel nature of the job execution on an FPGA. HDLs reflect some of the attributes of other textual languages, but they differ substantially because they are based on a dataflow model where I/O is connected to a series of function blocks through signals.  

HLS tools

We could achieve the performance advantages of specialized hardware without writing HDL if we could use these high-level languages, like C, for FPGA designs. High-Level Synthesis (HLS) technologies have been striving to accomplish this since the 1990s. Since then, HLS tools have substantially advanced and have industry support. Vivado HLS from AMD (formerly Xilinx), the Intel HLS Compiler, and SmartHLS from MicroChip are examples of industrial tools. Because these languages were intended to be converted into lists of instructions rather than circuits, these HLS compilers are frequently not flawless. Only a small percentage of C can be effectively converted into a circuit while maintaining the high-performance FPGAs are known for. Long 'if' statement chains run badly, however 'for' loops can be translated effectively. As a result, a new generation of tools has been developed that combine the use of CPUs with FPGAs. With this setup, the two might be combined on a single chip called a "system-on-chip" with shared memory. They could alternatively be independent chips connected by a PCI interface. This method is used by AMD's Vitis Unified Development environment and Intel's OneAPI.  

Tools specific to a domain

Domain-specific tools that create designs for certain purposes are another interesting topic. These tools are most frequently used in the machine learning field, where FPGA technology has shown great promise. Typically, these tools take a model from a well-known machine learning framework, such as PyTorch or TensorFlow, and provide an optimum architecture for that model. This translates to the fact that software writers can use FPGAS without any technical knowledge and still achieve excellent performance. For this, community resources include FINN and HLS4ML.  

Conclusion

There have been numerous attempts over the course of the FPGA industry's history to create better development languages than Verilog or VHDL. From neighborhood-based initiatives to create HDLs in more user-friendly programming languages to HLS tools that try to convert regular software code into high-performance hardware. The development of domain-specific tools that can provide efficient FPGA designs for certain applications, such as machine learning, has been the most successful development. FPGA technology is improved by these new tools and languages because they can deliver FPGA-level performance with a lot less work during development. Unfortunately, they can only do so under specific conditions. Due to their inherent ability to model circuits at the RTL level and their broad industry use, VHDL and Verilog still have a bright future. The best we as engineers can do is educate ourselves on these HDLs while remaining open-minded and willing to learn about and contribute to these new tools. By doing this, the FPGA community can grow and productivity may be increased.