AMD
XC2S100E-6FT256I
FPGAs (Field Programmable Gate Array)
XC2S100E-6FT256I
2-XC2S100E-6FT256I
FPGA Spartan-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 256-Pin FTBGA
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XC2S100E-6FT256I Description
Tech Specifications
Surface Mount
YES
Number of Pins
256
Combinatorial Delay of a CLB-Max
0.47 ns
Number of CLBs
600
Number of Logic Cells
2700
Number of Terminations
256
Operating Supply Voltage
1.8V
ECCN Code
EAR99
Supply Voltage-Max (Vsup)
1.89V
Number of Equivalent Gates
37000
Max Operating Temperature
100??C
Min Operating Temperature
-40??C
RAM Size
5kB
Clock Frequency
357MHz
Additional Feature
MAXIMUM USABLE GATES = 100000
HTS Code
8542.39.00.01
JESD-609 Code
e0
Programmable Logic Type
FIELD PROGRAMMABLE GATE ARRAY
Terminal Position
BOTTOM
Terminal Form
BALL
Peak Reflow Temperature (Cel)
240
Supply Voltage
1.8V
Pbfree Code
no
Terminal Pitch
1mm
Time@Peak Reflow Temperature-Max (s)
30
Pin Count
256
Moisture Sensitivity Level (MSL)
3 (168 Hours)
Speed Grade
6
Number of Outputs
202
Length
17mm
Height Seated (Max)
2mm
Width
17mm
Radiation Hardening
No
RoHS Status
Non-RoHS Compliant
XC2S100E-6FT256I Documents
Download datasheets and manufacturer documentation for XC2S100E-6FT256I
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