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Lattice Semiconductor_M5LV-512/160-12YC
Lattice Semiconductor_M5LV-512/160-12YC
Lattice Semiconductor

M5LV-512/160-12YC

FPGAs (Field Programmable Gate Array)
Lattice Semiconductor
M5LV-512/160-12YC
2-M5LV-512/160-12YC
CPLD MACH 5 Family 20K Gates 512 Macro Cells 52.6MHz/83.3MHz 3.3V 208-Pin PQFP Tray
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Description Tech Specifications Documents Shopping Guide

M5LV-512/160-12YC Description

Tech Specifications

Mounting Style
SMD/SMT
Delay Time
12 ns
Memory Type
EEPROM
Supply Voltage - Min
3 V
Minimum Operating Temperature
0 C
Number of Macrocells
512
Package / Case
PQFP-208
Operating Supply Voltage
3.3 V
Packaging
Tray
Number of Product Terms per Macro
32
Maximum Operating Frequency
71.4 MHz
Number of Programmable I/Os
48
Maximum Operating Temperature
+ 70 C
Supply Voltage - Max
3.6 V
Factory Pack Quantity
120

M5LV-512/160-12YC Documents

Download datasheets and manufacturer documentation for M5LV-512/160-12YC

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Shopping Guide

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