Lattice Semiconductor
M5-256/120-12YI
FPGAs (Field Programmable Gate Array)
M5-256/120-12YI
2-M5-256/120-12YI
CPLD MACH 5 Family 10K Gates 256 Macro Cells 52.6MHz/83.3MHz 5V 160-Pin PQFP Tray
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M5-256/120-12YI Description
CPLD MACH 5 Family 10K Gates 256 Macro Cells 52.6MHz/83.3MHz 5V 160-Pin PQFP Tray
Tech Specifications
Mounting Style
SMD/SMT
Delay Time
12 ns
Memory Type
EEPROM
Supply Voltage - Min
4.5 V
Minimum Operating Temperature
- 40℃
Number of Macrocells
256
Package / Case
PQFP-160
Operating Supply Voltage
4.5 V to 5.5 V
Packaging
Tube
Number of Product Terms per Macro
32
Maximum Operating Frequency
83.3 MHz, 100 MHz
Number of Programmable I/Os
120
Maximum Operating Temperature
+ 85℃
Supply Voltage - Max
5.5 V
Factory Pack Quantity
24
M5-256/120-12YI Documents
Download datasheets and manufacturer documentation for M5-256/120-12YI
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