Lattice Semiconductor
M4LV-64/32-10JC
FPGAs (Field Programmable Gate Array)
M4LV-64/32-10JC
2-M4LV-64/32-10JC
CPLD MACH 4 Family 2.5K Gates 64 Macro Cells 71.4MHz/95.2MHz 3.3V 44-Pin PLCC Tube
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M4LV-64/32-10JC Description
Tech Specifications
Mounting Style
SMD/SMT
Delay Time
10 ns
Memory Type
EEPROM
Supply Voltage - Min
3 V
Minimum Operating Temperature
0 C
Number of Macrocells
64
Package / Case
PLCC-44
Operating Supply Voltage
4.75 V to 5.25 V
Packaging
Tube
Number of Product Terms per Macro
20
Maximum Operating Frequency
111.1 MHz
Number of Programmable I/Os
32
Maximum Operating Temperature
+ 70 C
Supply Voltage - Max
3.6 V
Factory Pack Quantity
26
M4LV-64/32-10JC Documents
Download datasheets and manufacturer documentation for M4LV-64/32-10JC
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