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Lattice Semiconductor_M4LV-128/64-10YC
Lattice Semiconductor_M4LV-128/64-10YC
Lattice Semiconductor

M4LV-128/64-10YC  

FPGAs (Field Programmable Gate Array)
Lattice Semiconductor
M4LV-128/64-10YC
2-M4LV-128/64-10YC
CPLD MACH 4 Family 5K Gates 128 Macro Cells 71.4MHz/95.2MHz 3.3V 100-Pin PQFP Tray
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Description Tech Specifications Documents Shopping Guide

M4LV-128/64-10YC Description

CPLD MACH 4 Family 5K Gates 128 Macro Cells 71.4MHz/95.2MHz 3.3V 100-Pin PQFP Tray

Tech Specifications

Mounting Style
SMD/SMT
Delay Time
10 ns
Memory Type
EEPROM
Supply Voltage - Min
3 V
Minimum Operating Temperature
0 C
Number of Macrocells
128
Package / Case
PQFP-100
Operating Supply Voltage
4.75 V to 5.25 V
Packaging
Tube
Number of Product Terms per Macro
20
Maximum Operating Frequency
111.1 MHz
Number of Programmable I/Os
64
Maximum Operating Temperature
+ 70 C
Supply Voltage - Max
3.6 V
Factory Pack Quantity
66

M4LV-128/64-10YC Documents

Download datasheets and manufacturer documentation for M4LV-128/64-10YC

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Shopping Guide

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