Lattice Semiconductor
GAL26CV12B-10LP
FPGAs (Field Programmable Gate Array)
GAL26CV12B-10LP
2-GAL26CV12B-10LP
SPLD GAL Family 12 Macro Cells 105MHz 5V 28-Pin PDIP
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GAL26CV12B-10LP Description
Tech Specifications
Mounting Style
Through Hole
Operating Temperature
0 C to + 75 C
Supply Current
130 mA
Delay Time
10 ns
Supply Voltage - Min
4.75 V
Minimum Operating Temperature
0 C
Number of Macrocells
12
Package / Case
PDIP-28
Operating Supply Voltage
4.75 V to 5.25 V
Maximum Operating Frequency
105 MHz
Maximum Operating Temperature
+ 75 C
Logic Family
GAL
Supply Voltage - Max
5.25 V
Factory Pack Quantity
13
GAL26CV12B-10LP Documents
Download datasheets and manufacturer documentation for GAL26CV12B-10LP
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