Echelon Corporation
14235R-2000
Application Specific MCUs

$20.24

HC1S60F1020AA FPGAs Overview

HardCopy Stratix structured ASICs, Atera ‘s second-generatlon HardCopy structured ASICs, are low-cost, high-performance davices with the samearchitecture as the high-density Stratx FPGAs.The combinatlon of Stratk FPAs for prototyping and deslgn verficaton,HardCopy Stratix devicesor high-volume productlon, and the Quartus design sotware beghning w/th verslon 3.0, provide a complete and powerful atemative to ASICdeslgn and development
HardCopy Stratix HC1S60F1020AA devices are architecturaly equivalen! and have the same features as the coresponding Stratix FPGA. Theyofler pin-o-pin compatiblty using the same package as the corresponding Stratx FPCA protlype.Designers can prototype ther design to vertffunctionality with Stralx FPCAs belore seamlessly migrating the proven design to a HardCopy Stratix structured ASIC.
The Quartus l software provides a complete set of nexpenstve and easy-0-use tools for desgning HardCopy Stratx devices. Using the successfuland proven methodology from HardCopy APEX devices, Stratkx HC160F1020AA FPGA designs can be seamlessly and quckly migrated to a lo-cost ASIC alieative. Designers can use the Quartus ll sotvire to design HardCopy Stratix devices to obtain an average of 50% higherperformance and up o 40% owr power consumplion han can be achieved in the coresponding Stratix FPGAs, The migraion process is fulyautomated, roquros minimal customor invovement, and akes approxmalely cight weeks to delver fuly testod HardCopy Stratix prololypes.

Features

HardCopy Stratix devices are manufactured on the same 1.5-V, 0.13 um al-ayer-copper matal fabricathon process up to eight layers of metal) asthe Stratix FPGAS.
Preserves the functlonallty of a configured Stratix device
Pin-compatble wih the Stratix counterparts
On average, 50% faster than their Stratix equivalents
On average, 40% less power consumption than their Stratix equivalents
25 660 t0 79.040 LES
Up to 5.658 408 RAM bits available TiMatrix memory architecture consisting of three RAM block sizes to implement true dual-port memory and first-in-first-out (FIFO) bufers Embedded high speed DSP blocks provide dedicaled implementation of muipliers, mulliply accumulate functions, and finite impulse response(FIR) filters
” Up to 12 PLLs (four enhanced PLLs and eight fast PlLs) per device which provide idnfical features as the FPGA counterparts, induding spreadspecrum, programmabla bandxidth, clock switchover, rea-ime PLL reconfiguration, advanced muliplication, and phase shifing
Supports numerous singleended and diferential liO standards
Supports high-speed networking and comrmunications bus slandards including Rapidl0UTOPIA IV, CSIX,HyperTfransport technology,10GElhemnet XSB1, SPJ4 Phase 2 (POSPHY Lel 4), and SFI4
Differential on-chip termination support for LVOS